ASIC Design

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Information on ASIC design

ASIC design is interesting because it seems to not have caught up with Web3.0. There are maybe 2-3 YouTube videos that describe layout strategies, no one talks about ASIC design and anything else is on broken websites or theoretical academic papers with no practical, real-world use besides for companies who've already got a baseline down. Mostly, the layout procedure seems to be heavily missing in tutorials. There will be an abundant amount of resources on layout so that one can glean as much information from it as possible. This is an attempt at making learning ASIC design a smooth process into advanced topics.

Learning ASIC Design

One should have a basic understanding of assembly and what each instruction does. A general idea, rather than intimate knowledge behind a CPU should be simple enough to find online.


Some universities give all their classes out to the public. Thank you so much.

  • Harvey Mudd
    • The textbook is amazing and almost everyone uses it.
    • Lecture slides are good, but there is no video.
  • Las Vegas
    • There are almost 10 years of (video) lectures, homework assignments, and labs to be viewed here.
    • If you navigate his website, a good resource is under <year>/students/<student> since each student was required to make a website stepping through their work.
    • His cadence tutorials are a godsend and MTU's labs only go to his <emph>first</emph> tutorial. There are five after that.
  • NCSU (No longer public, but still has it)
    • No longer public, but available of
  • UC Davis
    • No longer public, but available on
    • The labs are of good quality.

Digital logic

Digital logic is the basic building blocks of ASIC design. A LUG lecture on this topic discussed the basics of digital logic, though it is recommended to follow the Harvey Mudd class on CPU architecture that was referenced in the lecture. The textbook (ISBN 978-0128200643) is a fantastic resource and worthy of a genuine purchase (though, it is on a certain library online). His MIPS version (ISBN 978-0123944245) is what MTU's computer organization class uses.

Hardware description languages (HDLs) are used to work with digital logic and generate CPUs. The main two languages used for HDL are Verilog and VHDL. One must use VHDL or Verilog to work with digital logic and is a requirement to continue forward. MTU teaches via Verilog, though the industry standard seems to be closed to VHDL. Choose whichever you deem fit. If you use a language outside of VHDL or Verilog, you will not be marketable (props to you, since I loathe the term "marketable").


1. Follow nand2tetris.

2. Design RISC-V CPU in Verilog. This is explained in ISBN 978-0128200643.

3. Design a 3-stage pipelined RISC-V CPU in Verilog (fetch, decode, execute). This is explained in ISBN 978-0128200643.



GTKWave is a visualization tool for debugging your HDL.


Icarus Verilog is a tool used to "compile" your Verilog code to be used in GTKWave. In actuality, IVerilog generates a netlist whereby GTKWave can use this netlist to simulate your circuit.

Layout of a chip

TODO: I'm not knowledgeable enough to know what steps to be done here.

Advanced topics

Analog circuits

Analog circuits require fundamental knowledge of MOSFETs, JFETs and BJTs. TODO: Give links.

Reverse engineering

Reverse engineering chips is really fascinating and gives a good idea as to how engineers laid out the chips without requiring you to sign an NDA before looking at any of the designs.

A list: